D-Latches, also referred to as transparent latches, are a key component of any synchronous or asynchronous digital circuit that needs to store data and keep it unchanged within a certain period of a clock cycle. In its most common form, a conventional D-latch circuit is an electronic data storage device with a data input, a clock (or a write enable input), and a data output. When a D-latch receives a clock signal that is at the latch's enable logic level, the latch is “transparent” and its output signal at its data output equals the input signal at the data input. If the clock signal is reversed, or disabled, the data output maintains the same output signal it had before the clock became disabled. This signal, or value, will be maintained until the next clock switch, or enablement. This capability of maintaining the value of the output signal makes latch circuits a building block for a plurality of logic circuits and electronic devices.
Typically, latch circuits comprise logic gates. In a latch, the logic gates may be connected in various configurations in order to perform logic operations with an input data signal and a clock signal. These logic operations evaluate the data signal and the clock signal and produce an output signal. At a physical level the logic gates comprise transistors. Complimentary paired transistors are configured in multiple types of configurations in order to create a specific logic gate.
Because transistors are made of semiconductor materials that do not withstand ions transitioning through them, radiation events (e.g., particle strikes) may cause one or more transistors within a latch to become conductive and change state from “off” to “on”. A radiation event, also referred to as a glitch, may initiate logical switching in a latch circuit which may result in two basic effects: a Single Event Transient (SET) or a Single Event Upset (SEU). Typically, within the duration of a glitch, a disturbed transistor will recover back to its off-state unless its control voltage level has been affected by the glitch.
The first effect, SET, by definition, is a glitch logically propagated from an affected node to the latch output. If such a glitch gets logically latched-in inside the latch and its output does not recover until the next clock cycle or enable signal then this effect becomes the second type of effect: an SEU or soft error. SEU events, more so than SET events, may be detrimental to a latch and circuits relying on the latch. The wrong output signal at the data output of a latch could cause circuits relying on the latch to be delayed or locked-up.
Therefore, a hardened latch is presented that prevents SEUs in the event of a SET.